september 2013 dsc-3210/11 1 ?2013 integrated device technology, inc. features 64k x 16 advanced high-speed cmos static ram equal access and cycle times ? commercial : 12/15/20ns ? industrial: 15/20ns one chip select plus one output enable pin bidirectional data inputs and outputs directly ttl- compatible low power consumption via chip deselect upper and lower byte enable pins commercial and industrial product available in 44-pin plastic soj package and 44-pin tsop package description the idt71016 is a 1,048,576-bit high-speed static ram organized as 64k x 16. it is fabricated using high-perfomance, high-reliability cmos technology. this state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. the idt71016 has an output enable pin which operates as fast as 7ns, with address access times as fast as 12ns. all bidirectional inputs and outputs of the idt71016 are ttl-compatible and operation is from a single 5v supply. fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. the idt71016 is packaged in a jedec standard 44-pin plastic soj and 44-pin tsop type ii. functional block diagram output enable buffer address buffers chip enable buffer write enable buffer byte enable buffers oe a0 - a15 row / column decoders cs we bhe ble 64k x 16 memory array sense amps and write drivers 16 low byte i/o buffer 8 8 8 8 i/o 8 i/o 15 i/o 7 i/o 0 3210 drw 01 high byte i/o buffer , cmos static ram 1 meg (64k x 16-bit) idt71016s
6.42 2 idt71016, cmos static ram 1 meg (64k x 16-bit) commercial and industrial temperature ranges pin configurations soj/tsop top view truth table (1) pin descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 i/o 7 nc a12 a13 a14 a15 we i/o 6 i/o 5 i/o 4 v ss v cc i/o 3 i/o 2 i/o 1 i/o 0 cs a0 a1 a2 a3 a4 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a6 a7 oe bhe ble i/o 15 i/o 14 i/o 13 i/o 12 v ss v cc i/o 11 i/o 10 i/o 9 i/o 8 a8 a9 a10 a11 nc a5 nc so44-1 so44-2 3210 drw 02 , a 0 - a 15 address inputs input cs chip select input we write enable input oe output enable input bhe high byte enable input ble low byte enable input i/o 0 - i/o 15 data input/output i/o v cc 5.0v power pwr v ss ground gnd 3210 tbl 01 note: 1. h = v ih , l = v il , x = don't care. cs oe we ble bhe i/o 0 - i/o 7 i/o 8 - i/o 15 function h x x x x high-z high-z deselected - standby l l h l h dataout high-z low byte read l l h h l high-z dataout high byte read l l h l l dataout dataout` word read l x l l l datain datain word write l x l l h datain high-z low byte write l x l h l high-z datain high byte write l h h x x high-z high-z outputs disabled l x x h h high-z high-z outputs disabled 3210 tbl 02
6.42 idt71016, cmos static ram 1 meg (64k x 16-bit) commercial and industrial temperature ranges 3 dc electrical characteristics (1) (v cc = 5.0v 10%, v lc = 0.2v, v hc = v cc ?0.2v) absolute maximum ratings (1) capacitance (t a = +25 c, f = 1.0mhz, soj/tsop package) recommended dc operating conditions dc electrical characteristics (v cc = 5.0v 10%, commercial and industrial temperature range) note: 1. v il (min.) = ?1.5v for pulse width less than trc/2, once per cycle. symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ v dd +0.5 v v il input low voltage -0.5 (1 ) ____ 0.8 v 3210 tbl 05 note: 1. this parameter is guaranteed by device characterization, but not production tested. symbol parameter (1 ) conditions max. unit c in input capacitance v in = 3dv 6 pf c i/o i/o capacitance v out = 3dv 7 pf 3210 tbl 06 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v cc + 0.5v. symbol rating value unit v term (2) terminal voltage with respect to gnd -0.5 to +7.0 v t bias te m p e r a tu r e under bias -55 to +125 o c t stg storage te m p e r a tu r e -55 to +125 o c p t power dissipation 1.25 w i out dc output current 50 ma 3210 tbl 03 symbol parameter test conditions min. max. unit |i li | input leakage current v cc = max., v in = gnd to v cc __ _ 5a |i lo | output leakage current v cc = max., cs = v ih , v out = gnd to v cc __ _ 5a v ol output low voltage i ol = 8ma, v cc = min. __ _ 0.4 v v oh output high voltage i oh = -4ma, v cc = min. 2.4 ___ v 3210 tbl 07 notes: 1. all values are maximum guaranteed values. 2. f max = 1/t rc (all address inputs are cycling at f max ); f = 0 means no address input lines are changing . 71016s12 71016s15 71016s20 symbol parameter com'l. com'l. ind. com'l. ind. unit i cc dynamic operating current cs < v il , outputs open, v cc = max., f = f max (2) 210 180 180 170 170 ma i sb standby power supply current (ttl level) cs > v ih , outputs open, v cc = max., f = f max (2) 60 50 50 45 45 ma i sb1 standby power supply current (cmos level) cs > v hc , outputs open, v cc = max., f = 0 (2) v in < v lc or v in > v hc 10 10 10 10 10 ma 3210 tbl 08 grade temperature gnd v cc commercial 0c to +70c 0v 5.0v 10% industrial ?40c to +85c 0v 5.0v 10% 3210 tbl 04 recommended operating temperature and supply voltage
6.42 4 idt71016, cmos static ram 1 meg (64k x 16-bit) commercial and industrial temperature ranges ac test conditions figure 1. ac test load figure 2. ac test load (for t clz , t olz , t chz , t ohz , t ow, and t whz ) *including jig and scope capacitance. figure 3. output capacitive derating ac test loads 1 2 3 4 5 6 7 20 40 60 80 100 120 140 160 180 200 t aa, t acs (typical, ns) capacitance (pf) 8 3210 drw 05 ? ? ? ? ? ? ? , 3210 drw 04 480 255 5pf* data out 5v , 480 255 30pf* data out 5v 3210 drw 03 , input pulse levels input rise/fall times input timing reference levels output reference levels ac test load gnd to 3.0v 1.5ns 1.5v 1.5v see figure 1, 2 and 3 3210 tbl 09
6.42 idt71016, cmos static ram 1 meg (64k x 16-bit) commercial and industrial temperature ranges 5 timing waveform of read cycle no. 1 (1,2,3) notes: 1. we is high for read cycle. 2. device is continuously selected, cs is low. 3. oe , bhe , and ble are low. ac electrical characteristics ( v cc = 5.0v 10%, commercial and industrial range ) data out address 3210 drw 06 t rc t aa t oh t oh data out valid previous data out valid , note: 1. this parameter is guaranteed with the ac load (figure 2) by device characterization, but is not production tested. 2. 12ns commercial only. 71016s12 (2) 71016s15 71016s20 symbol parameter min. max. min. max. min. max. unit read cycle t rc read cycle time 12 ____ 15 ____ 20 ____ ns t aa address access time ____ 12 ____ 15 ____ 20 ns t acs chip select access time ____ 12 ____ 15 ____ 20 ns t clz (1) chip select low to output in low-z 4 ____ 5 ____ 5 ____ ns t chz (1) chip select high to output in high-z ____ 6 ____ 6 ____ 8ns t oe output enable low to output valid ____ 7 ____ 8 ____ 10 ns t olz (1) output enable low to output in low-z 0 ____ 0 ____ 0 ____ ns t ohz (1) output enable high to output in high-z ____ 6 ____ 6 ____ 8ns t oh output hold from address change 4 ____ 4 ____ 5 ____ ns t be byte enable low to output valid ____ 7 ____ 8 ____ 10 ns t blz (1) byte enable low to output in low-z 0 ____ 0 ____ 0 ____ ns t bhz (1) byte enable high to output in high-z ____ 6 ____ 6 ____ 8ns wri te cycle t wc write cycle time 12 ____ 15 ____ 20 ____ ns t aw address valid to end of write 9 ____ 10 ____ 12 ____ ns t cw chip select low to end of write 9 ____ 10 ____ 12 ____ ns t bw byte enable low to end of write 9 ____ 10 ____ 12 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wr address hold from end of write 0 ____ 0 ____ 0 ____ ns t wp write pulse width 9 ____ 10 ____ 12 ____ ns t dw data valid to end of write 7 ____ 8 ____ 10 ____ ns t dh data hold time 0 ____ 0 ____ 0 ____ ns t ow (1) write enable high to output in low-z 1 ____ 1 ____ 1 ____ ns t whz (1) write enable low to output in high-z ____ 6 ____ 6 ____ 8ns 3210 tbl 10
6.42 6 idt71016, cmos static ram 1 meg (64k x 16-bit) commercial and industrial temperature ranges timing waveform of read cycle no. 2 (1) notes: 1. a write occurs during the overlap of a low cs , low bhe or ble , and a low we . 2. oe is continuously high. if during a we controlled write cycle oe is low, t wp must be greater than or equal to t whz + t dw to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified t wp . 3. during this period, i/o pins are in the output state, and input signals must not be applied. 4. if the cs low or bhe and ble low transition occurs simultaneously with or after the we low transition, the outputs remain in a high-impedance state. 5. transition is measured 200mv from steady state. timing waveform of write cycle no. 1 ( we controlled timing) (1,2,4) notes: 1. we is high for read cycle. 2. address must be valid prior to or coincident with the later of cs , bhe , or ble transition low; otherwise t aa is the limiting parameter. 3. transition is measured 200mv from steady state. address data out 3210 drw 07 (3) (3) (3) data valid t aa t rc t oe t olz t chz t ohz out (3) t acs (3) t blz t clz (2) t be t oh t bhz (3) (2) , oe cs bhe , ble address cs data in 3210 drw 08 (5) (5) (5) data in valid t wc t as t whz (2) t cw t chz t ow t wr we t aw data out t dw t dh previous data valid data valid bhe , ble t bw t wp (5) t bhz (3) ,
6.42 idt71016, cmos static ram 1 meg (64k x 16-bit) commercial and industrial temperature ranges 7 timing waveform of write cycle no. 2 ( cs controlled timing) (1,4) notes: 1. a write occurs during the overlap of a low cs , low bhe or ble , and a low we . 2. oe is continuously high. if during a we controlled write cycle oe is low, t wp must be greater than or equal to t whz + t dw to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified t wp . 3. during this period, i/o pins are in the output state, and input signals must not be applied. 4. if the cs low or bhe and ble low transition occurs simultaneously with or after the we low transition, the outputs remain in a high-impedance state. 5. transition is measured 200mv from steady state. timing waveform of write cycle no. 3 ( bhe , ble controlled timing) (1,4) address cs data in 3210 drw 9 data in valid t wc t as (2) t cw t wr we t aw data out t dw t dh bhe , ble t bw t wp , address cs data in 3210 drw 10 data in valid t wc t as (2) t cw t wr we t aw data out t dw t dh bhe , ble t bw t wp ,
6.42 8 idt71016, cmos static ram 1 meg (64k x 16-bit) commercial and industrial temperature ranges ordering information s power xx speed xxx package x process/ temperature range blank i commercial (0c to +70c) industrial (-40c to +85c) y ph 400-mil soj (so44-1) 400-mil tsop type ii (so44-2) 12 * 15 20 71016 device type speed in nanoseconds 3210 drw 11 x g green blank 8 tube or tray tape and reel x * commercial temperature range only
6.42 idt71016, cmos static ram 1 meg (64k x 16-bit) commercial and industrial temperature ranges 9 the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 07/30/99: updated to new format 080/5/99: pg. 3 expressed commercial and industrial ranges on dc electrical table removed icc, i sb , and i sb 1 values for s12 industrial speed pg. 5 expressed commercial and industrial ranges on ac electrical table changed footnote #2 to commercial temperature only pg. 6 revised footnotes on write cycle no.1 diagram pg. 7 revised footnotes on write cycle no.2 and no.3 diagrams pg. 8 removed scd 2752 footnote added commercial only for 12ns speed 08/13/99: pg. 9 added datasheet document history 09/30/99: pg. 3, 5, 8 added 12ns industrial temperature speed grade offering 08/09/00: not recommended for new designs 02/01/01: removed "not recommended for new designs" 01/30/04: pg. 8 added "restricted hazardous substance device" to order information 01/30/06: pg. 3 updated capacitance table to include tsop 02/13/07: pg. 8 added n generation die step to data sheet ordering information 10/13/08: pg. 8 removed "idt" from orderable part number 09/25/13: pg. 1 updated commercial and industrial speed grade offerings removed idt reference to fabrication pg. 3 removed commercial t a information from the absolute maximum ratings table removed ind. temp values for the 12ns speed grade from the dc elec chars table pg. 5 added the footnote annotation to the ac elec chars table and the footnote for 12ns commercial only pg. 8 added t & r to, updated restricted hazardous substance device wording to "green", added annotation indicating "commercial temperature range only" and removed die stepping indicator from the ordering information corporate headquarters for sales: 6024 silver creek valley road 800-345-7015 or san jose, ca 95138 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: sramhelp@idt.com 408-284-4532
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